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2021-06-18T13:46:16+09:00
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Ritsumeikan Univ.KO-580
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(A study on reliability enhancement of power and circuit operation in VLS\
I)Tj
/TT1 1 Tf
12 0 0 12 457.0176 759.75 Tm
(Yoshiyuki Kawakami)Tj
-34.376 -2.313 Td
(With the advent of the deep submicron age, it becomes possible to implem\
ent high performance and large-)Tj
-1 -1.5 Td
(scale system LSIs. At the same time, there are problems of signal integr\
ity and power integrity, and)Tj
0 -1.5 TD
(manufacturing variation of transistor size and threshold voltage are inc\
reasing. These trends make dependable)Tj
T*
(operation of LSI circuit difficult. To improve the dependability of the \
circuit operation of LSI, it is so)Tj
T*
(necessary to construct a robust power design methodology that the circui\
t doesn't malfunction even when the)Tj
T*
(manufacturing variation is caused.)Tj
T*
(First, a power design optimization method that can obtain an optimal sol\
ution with high dependability as a)Tj
T*
(whole circuit is proposed even when the manufacturing variation is cause\
d. The method not only treats IR)Tj
T*
(drop, the electro migration and the wiring area, etc. as constraints but\
also aims to obtain a safer solution than)Tj
T*
(a design constraint satisfaction. The common concept like design risk an\
d safety is introduced for these plural)Tj
T*
(design goals that exist in the trade-off relation, and high safety can b\
e secured by the multi-objective)Tj
T*
(optimization.)Tj
T*
(Next, a power design optimization that can consider the circuit delay va\
riation due to the manufacturing)Tj
T*
(variation and IR drop is implemented. The new design risk indicates rati\
o in danger which causes the)Tj
T*
(manufacturing variation, IR drop and timing error, and a modeling method\
that relates among them is)Tj
T*
(constructed. Therefore a power design optimization observing timing erro\
r risk directly can be implemented.)Tj
T*
(In addition, another one observing timing error risk of critical path di\
rectly is implemented by combining)Tj
T*
(with the statistical static timing analysis.)Tj
T*
(This effectiveness is shown by the experiments. As a result, since a pow\
er design optimization that considers)Tj
T*
(the circuit delay variation due to the manufacturing variation and IR dr\
op is implemented, the power design)Tj
T*
(methodology can be achieved robustness and high reliability.)Tj
ET
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